Flash memories are widely known in the related art as semiconductor nonvolatile memory devices ideal for storing data in portable form. The cost per flash memory bit sharply decreases each year and this decrease is even steeper than projected from only a steadily reduced memory size. This decreased cost is due to improvements in the device structure or to use of multilevel storage. Technology of the prior art relating to large capacity flash memories for file applications is disclosed for example in F. Arai, et al., IEEE International Electron Devices Meeting pp. 775-778, 2000 (non-patent document 2) and in T. Kobayashi et al., IEEE International Electron Devices Meeting pp. 29-32, 2001 (non-patent document 1). The former method utilized a structure called a NAND gate designed to yield a small cell size. The latter method utilized a structure called an AND gate designed for multilevel storage operation to control the number of electrons stored inside the floating gate to store large numbers of bits. Both of these methods were effective in reducing the cost.
Another example of multilevel storage is disclosed in B. Eitan et al., International Conference on Solid State Devices and Materials pp. 522-524, 1999 (non-patent document 3). In this method, a device injects electrical charges by hot electrons, utilizing SiN in the storage region. This method utilizes the electrical charges that accumulate in the vicinity of the location where the charges are injected due to electrical charges that accumulate in the SiN trap, and also the hot electrons emitted mainly in the vicinity of the drain terminal. Both the source terminal and the drain terminal are utilized as the electrical charge storage region by interchanging the voltages applied to the source and the drain. This program (write) method requires a large electrical current flow and the current supplied by the power supply is limited and so is not suited for file applications where numerous bits are being programmed (written) at the same time. A programming operation for injection on the source side with a lower drain current is disclosed in JP-A No. 156275/2001 (patent document 1). This technology achieves a small cell size and utilizes auxiliary electrodes for injection on the source side in an operation utilizing an inversion layer below the auxiliary electrode as the wiring.
[Patent document 1] JP-A No. 156275/2001
[Non-patent document 1] F. Arai. et al., IEEE International Electron Devices Meeting pp. 775-778, 2000
[Non-patent document 2] T. Kobayashi et al., IEEE International Electron Devices Meeting pp. 29-32, 2001
[Non-patent document 3] B. Eitan et al., International Conference on Solid State Devices and Materials pp. 522-524, 1999
A lower cost per bit in flash memories was achieved by improving the device structure or by utilizing multilevel storage to reduce the memory size through patterning method size reduction. The increased capacity of the flash memory also ensures an expanding range of applications for handling large size files such as music and moving picture files. The demand for large capacity flash memories also having a fast program (writing) speed is likely to grow even larger from hereon.
However, the structure of NAND type devices are nearing a surface area of 4F2 (F is the patterning dimension) per cell which is the logical limit on flat (planar) memory cell structures. It will prove difficult to make the cell surface area any smaller than this dimension. This fact suggests further progress is needed in multilevel storage. Further problems are that the program (write) speed is not fast because the Fowler-Nordheim (hereafter abbreviated to FN) tunnel is utilized for programming, or that large voltages must be utilized.
However, hot electron programming technology using AND device can be utilized for high speed programming. This technology utilizes the source injection method for hot electron programming (writing) and so is suited for simultaneous programming of many cells. Moreover, the array structure utilizes parallel connections without the serial connections used in the NAND type device. The AND type device is therefore much less susceptible to effects from memory information of other cells, and is suited for large bit storage per cell. However, there are problems with this AND device. In terms of cell size, the diffusion layers in the array structure extend in parallel so that this device has the problem that the vertical pitch in the word lines is difficult to shrink (reduce) due to widening of the diffusion layer or the device isolation regions. Moreover, when using the source injection method for hot electron programming, variations occurs in the voltage set for the auxiliary electrode and cause the problem of non-uniform cell programming characteristics. Further, in the AND type device, the memory cells are connected in parallel with the local data line so that the distance to the contact differs according to the memory cell position. The voltage on the local data line therefore drops, causing the voltage potential applied to the cell to fluctuate and causing the problem of variations (non-uniformities) in cell programming characteristics.